![modelsim altera starter edition 10.3d modelsim altera starter edition 10.3d](https://blog.kakaocdn.net/dn/sjw4h/btqysNBtEZr/AyZJ6OQFeNJq7EdaFNqEx0/img.png)
The design consist of only one transceiver channel with fixed 16 bits data pattern. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The purpose of this design example is to assist users to have quick start with the Cyclone V transceivers.
![modelsim altera starter edition 10.3d modelsim altera starter edition 10.3d](https://coldnew.github.io/ce6f7a0a/Screenshot_20180607_004559.png)
#Modelsim altera starter edition 10.3d manual#
This basic design example with Modelsim simulation demonstrates the implementing of Cyclone V Native PHY with manual alignment and byte ordering in single-width mode. The design also come with example test bench and TCL file to run simulation in Modelsim for reference.Ĭyclone V Native PHY with bit slip alignment design example QII v15.0 (ZIP)Ĭyclone V Native PHY with manual alignment and byte ordering in single width mode design example Overview You should create your own bit slip controller. Note the bit slip controller is just for reference only. The design consist of only one transceiver channel with fixed synchronization pattern. This basic design example with Modelsim simulation demonstrates the implementing of Cyclone V Native PHY with bit slip alignment. Native PHY IP, Transceiver Reconfiguration Controller, Transceiver PHY Reset ControllerĬyclone V Native PHY with bit slip alignment design example Overview Note that you should create your own word aligment controller as the control is done in test bench in the example.Ĭyclone V Native PHY with manual alignment design example QII v15.0 (ZIP) Design Specifications The design consist of only one transceiver channel with data pattern switch between synchronization and incremental pattern. This basic design example with Modelsim simulation demonstrates the implementing of Cyclone V Native PHY with manual alignment. The table below lists the specifications for this design: AttributeĬustom PHY IP, Transceiver Reconfiguration ControllerĬyclone V Native PHY with manual alignment design example Overview Type "simulate" to start simulation Design FileĬyclone V Custom PHY with automatic synchronization state machine design example QII v15.0 (ZIP) Design Specifications Change the Modelsim directory to the unzipped folderĥ. The design also come with example test bench and TCL file to run simulation in Modelsim for reference.Ģ. This basic design example with Modelsim simulation demonstrates the implementing of Cyclone V Custom PHY with automatic synchronization state machine. Cyclone V Transceiver PHY Basic Design ExamplesĬyclone V Custom PHY with automatic synchronization state machine design example Overview